Title :
Increased CMOS IC stuck-at fault coverage with reduced I DDQ test sets
Author :
Fritzemeier, Ronald R. ; Soden, Jerry M. ; Treece, R. Keith ; Hawkins, Charles F.
Author_Institution :
Sandia Nat. Lab., Albuquerque, NM, USA
Abstract :
The authors discuss the significant improvements that were achieved when a conventional ATPG (automatic test pattern generation) algorithm was modified to generate test sets suitable for IDDQ testing. These improvements include increased SAF (stuck-at-fault) coverage, reduced vector set sizes, coverage of logically redundant SAFs and multiple SAFs, increased coverage of CMOS IC non-SAF defects, and reduced CPU cost for ATPG and fault simulation. This reduction in computational complexity for IDDQ based ATPG enables test generation for much larger circuits than previously possible. Additionally untestable faults can be further categorized to identify SAFs that are truly `don´t-care faults,´ thereby offering a more realistic assessment of actual fault coverage
Keywords :
CMOS integrated circuits; automatic testing; digital simulation; fault location; integrated circuit testing; logic testing; CMOS IC; CPU cost; automatic test pattern generation; automatic testing; computational complexity; don´t-care faults; fault simulation; reduced IDDQ test; stuck-at fault coverage; stuck-at-fault; vector set sizes; Automatic test pattern generation; Automatic testing; CMOS integrated circuits; Central Processing Unit; Circuit faults; Circuit testing; Computational modeling; Costs; Integrated circuit testing; Test pattern generators;
Conference_Titel :
Test Conference, 1990. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-9064-X
DOI :
10.1109/TEST.1990.114051
