Criteria for analyzing high frequency testing performance of VLSI automatic test equipment

It is pointed out that the development of higher speed CMOS VLSI, specifically RISC (reduced-instruction-set computer) and CISC (complex-instruction-set computer), places added demands on the high-frequency test capabilities of ATE (automatic test equipment) used to test these components. The author analyzes the attributes of the tester pin electronics and the DUT- (device-under-test-) to-tester interface, and proposes new ATE requirements in these areas. The following issues are discussed: maintaining tester timing accuracy at the DUT pin, testing high-speed CMOS devices with low output impedance, analyzing comparator input capacitance effects, and the importance of a short tester-to-DUT interface. It is concluded that the actual signal frequency capability of the system, which includes improved timing accuracy, as well as specific solutions to the DUT interface limitations, must be addressed and solved