Validated methodology for short-design-cycle chip, package and system interaction

While in the past, the silicon, package and system could be designed sequentially, at silicon nodes less than 40nm, the interconnects between the chip, package and system are becoming the limiting factor in performance and reliability. Hardware designers need to know upfront, what tradeoffs they need to make, to design an optimal system level solution. Quantitative estimates on the optimal package materials, assembly processes and design rules are required upfront as opposed to much later in the design process: In the past, several iterations of learning cycle test vehicles and modeling were used to address some of these questions, but with design cycles shrinking to less than a year in some cases, there is no time for repeated learning cycles and qualitative numerical models that only give general trends. Consequently, the industry needs a methodology that can give optimal Chip Package System Interaction (CPSI) design parameter ranges and reduce the number of prototype iterations. A key requirement in CPSI is the ability to accurately scale from chip level interconnects (on the order of a few microns), to system level features (on the order of several millimeters). Historically, CPSI has been evaluated using conventional finite element models in which smeared or submodeling techniques were used to approximate the mechanics of the assembly. Such approximations were necessary to achieve manageable computation times. However, these approximations have relegated the numerical models to qualitative trend assessments as opposed to a more regimented quantitative analysis. In this paper, a complete methodology is presented, that can more accurately capture the mechanics of CPSI without requiring unreasonable computation time for multiple design iterations. The methodology is a combination of experimental evaluation and numerical analysis. Both used iteratively achieve the intended purpose: reduce overall design time with less cost and design iterations giving quantitative- estimates. Each process step, starting from chip attach and ending with ball attach and board level assembly, was experimentally characterized for the 40nm silicon node Bill of Materials (BOM) and compared against numerical models. The iterative experimental correlation and the resulting model methodology are outlined in detail in this paper. Having experimentally validated the methodology, the effects of chip thickness, substrate thickness, bump design, underfill material, lid, stiffener and lid attachment on package warpage were determined and compared with experimental data. The corresponding impact of these factors on bump fatigue life and die level stresses was also determined. The relationship between board level assembly parameters and package and chip design variables was also determined. Finally, next generation on-demand cloud computing resources were used to further reduce computation times without sacrificing accuracy. A parametric study of the computing resources and processing times was also performed to help designers select the best computing resources for optimal design for faster times to market and product reliability.