Title :
A rate-controllable near-lossless data compression IP for HDTV decoder LSI in 65nm CMOS
Author :
Uchiyama, Masato ; Oikawa, Kohei ; Date, Naoto ; Koto, Shinichiro
Author_Institution :
Center for Semicond. R&D, Toshiba Semicond. Co., Kawasaki, Japan
Abstract :
We propose a rate-controllable near-lossless embedded compression algorithm "TLS-1". The algorithm guarantees a selected compression ratio with the smart combination of variable length coding and fixed length coding. It achieves near-lossless image quality under CR = 2. We apply the algorithm to an IP in an HDTV decoder LSI in order to reduce the required external memory capacity and its bandwidth. The LSI is fabricated in a 65 nm CMOS technology.
Keywords :
CMOS integrated circuits; IP networks; data compression; high definition television; image coding; large scale integration; variable length codes; CMOS; HDTV decoder LSI; IP; TLS-1; fixed length coding; rate-controllable near-lossless data compression; size 65 nm; variable length coding; Bandwidth; CMOS technology; Chromium; Compression algorithms; Data compression; Decoding; HDTV; Image coding; Image quality; Large scale integration;
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
DOI :
10.1109/ASSCC.2009.5357148
