Direct access test scheme-design of block and core cells for embedded ASICs

Author

Immaneni, Venkata ; Raman, Srinivas

Author_Institution

Intel Corp., Chandler, AZ, USA

fYear

1990

fDate

10-14 Sep 1990

Firstpage

488

Lastpage

492

Abstract

Intel requires the use of a direct-access test scheme in embedded-core or block-based ASIC (application-specific integrated-circuit) designs. This scheme provides for separate testing of individual block or core cells using proven test vectors. The authors discuss the design modifications for block cells with low pin counts, user application blocks, and large cores with high pin counts. The implementation and verification of the direct-access test scheme in a block- or core-based embedded ASIC design are also briefly described

Keywords

application specific integrated circuits; automatic testing; integrated circuit testing; logic CAD; logic testing; IC testing; Intel; VLSI; application-specific integrated-circuit; block cells; block-based ASIC; core cells; direct-access test; embedded ASICs; logic testing; test vectors; user application blocks; Application specific integrated circuits; Circuit testing; Flexible printed circuits; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit testing; Logic circuits; Logic testing; Pins; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1990. Proceedings., International

Conference_Location

Washington, DC

Print_ISBN

0-8186-9064-X

Type

conf

DOI

10.1109/TEST.1990.114058

Filename

114058