DocumentCode
2723459
Title
Tera-scale performance image stream processor with SoC architecture for multimedia content analysis
Author
Chen, Tse Wie ; Tang, Chi Sun ; Tsai, Sung Fang ; Tsai, Chen Han ; Chien, Shao Yi ; Chen, Liang Gee
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2009
fDate
16-18 Nov. 2009
Firstpage
189
Lastpage
192
Abstract
A 1.0 TOPS image stream processor, which deals with image processing tasks for multimedia content analysis, is implemented with 2.2 mm2 area in 90 nm CMOS technology. Two sub processors, linear processor and order processor, are integrated to achieve tera-scale performance. In the proposed SoC architecture, the data are transferred between processors and the high bandwidth dual memory through the local media bus, which reduces the power consumption in the AHB data access. Based on the memory architecture, the maximum input data rate of the proposed image stream processor reaches 62.5 Gpixel/s, which meets the requirements for real-time HDTV image processing.
Keywords
CMOS integrated circuits; image processing; multimedia communication; system-on-chip; AHB data access; CMOS technology; HDTV image processing; SoC architecture; TOPS image stream processor; high-bandwidth dual memory; linear processor; local media bus; multimedia content analysis; order processor; sub processors; system-on-chip; terascale performance; Bandwidth; CMOS process; CMOS technology; Energy consumption; HDTV; Image analysis; Image processing; Memory architecture; Performance analysis; Streaming media;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location
Taipei
Print_ISBN
978-1-4244-4433-5
Electronic_ISBN
978-1-4244-4434-2
Type
conf
DOI
10.1109/ASSCC.2009.5357149
Filename
5357149
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