DocumentCode :
2723587
Title :
An architecture for high-speed analog in-circuit testing
Author :
Klein, Larry ; Bridgeman, John
Author_Institution :
Teradyne Inc., Boston, MA, USA
fYear :
1990
fDate :
10-14 Sep 1990
Firstpage :
562
Lastpage :
564
Abstract :
Conventional analog in-circuit tests run considerably slower than digital ones, putting throughput at risk as circuit boards incorporate more analog components. The authors describe a novel architecture in which distributed processors work in parallel to dramatically speed analog testing. This architecture uses distributed digital-signal-processing chips operating independently and in parallel to achieve a sevenfold improvement in analog in-circuit test throughput over conventional test approaches. Design efforts concentrated on efficient use of the distributed processors in handling matrix-resource allocation and all analog test functions, and on minimizing physical effects that could inhibit test speed
Keywords :
analogue circuits; digital signal processing chips; integrated circuit testing; linear integrated circuits; parallel architectures; printed circuit testing; circuit boards; computer architecture; distributed digital-signal-processing chips; distributed processors; high-speed analog in-circuit testing; matrix-resource allocation; parallel architecture; Circuit testing; Delay; Dielectric measurements; Logic devices; Logic testing; Resistors; System testing; Throughput; Time measurement; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1990. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-9064-X
Type :
conf
DOI :
10.1109/TEST.1990.114068
Filename :
114068
Link To Document :
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