Towards a standard approach for controlling board-level test functions

The architecture and some of the specific features of a scan-and-clock resource (SCR) chip are described. This chip is used in a high-end workstation product to provide access to the testability features of the individual chips and or printed circuit boards. The chip is designed to be included on each system board and is capable of controlling up to eight independent scan ports. By careful examination of different scan styles, it was discovered that there are two basic styles of scan, differentiated by their clocking mechanisms. The SCR chip uses a mode bit to specify the scan style for each port separately and by so doing to convert from the actual scan style to an internal style so that actual chip characteristics are hidden from the scan/diagnostics software. It is pointed out that using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) are emerging as a common strategy for designing testable digital systems. On the basis of experience gained from such an application, controller features which are deemed useful are discussed