Title :
A delay-locked loop with digital background calibration
Author :
Lin, Wei Ming ; Teng, Kuang Fu ; Liu, Shen Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A delay-locked loop (DLL) with digital background calibration is presented. The static phase error of a DLL may exist owing to the current mismatch in the charge pump (CP). A digital background calibration using the time amplifier is presented. This DLL is fabricated in a CMOS 0.18 ¿m technology. The measured input frequency range of this DLL is from 400 MHz to 525 MHz. The measured static phase error without and with calibration is 113.8 ps and 27.8ps, respectively, at 525 MHz. The measured peak-to-peak jitter without and with calibration is 15.56 ps and 15.11 ps, respectively. The power consumption is 25.2 mW at 500 MHz and the area is 0.85 mm2.
Keywords :
CMOS digital integrated circuits; amplifiers; calibration; delay lock loops; jitter; CMOS technology; DLL; charge pump; current mismatch; delay-locked loop; digital background calibration; frequency 400 MHz to 525 MHz; input frequency range; peak-to-peak jitter; power consumption; size 0.18 mum; static phase error; time amplifier; CMOS technology; Calibration; Charge pumps; Clocks; Counting circuits; Delay effects; Jitter; Phase frequency detector; Phase locked loops; Voltage control;
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
DOI :
10.1109/ASSCC.2009.5357157
