Numerical and experimental characterization of the thermal behavior of a packaged DRAM-on-logic stack

3D-TSV technologies promise increased system integration at lower cost and reduced footprint. One of the most likely applications of 3D technology is the integration DRAM-on-logic. Thermal management issues are considered one of the potentially showstoppers for 3D-integration. In this paper, we present a thermal experimental and modeling characterization of a packaged DRAM on logic stack. The DRAM die is stacked to the thinned logic die (25μm) using CuSn microbumps. For the experimental characterization a dedicated logic chip with integrated heaters and sensors is used. The thermal impact of logic hot spot dissipation on the temperature profile of the DRAM and the logic die is experimentally characterized in a dedicated socket using two experimental configurations mimicking a high power and a low power configuration respectively. The use of those 2 different experimental configurations of the packaged stack allows the calibration of a detailed finite element thermal model. The calibrated thermal models are used to evaluate the impact of the effective thermal conductivity of the microbump and underfill layer and the impact of the logic die thickness on the temperature distribution in the logic and DRAM die for different cooling configurations of the die stack.