Jitter minimization technique for mixed signal testing

The authors describe a high-frequency clock source using jitter reduction circuitry to minimize the effect of problems in test and measurement systems. A mathematical explanation of the errors imposed by jitter is presented, along with a discussion of the hardware used to minimize its effects. Test results that demonstrate the benefit of the jitter minimization technique are provided. A reduction in the jitter of a clock signal from 100 ps peak to peak to 10 ps peak to peak has been realized by using this technique. This results in a direct improvement in AC measurement accuracy when low jitter clocks are used as conversion start signals