DocumentCode :
2723687
Title :
An integrated linear regulator with fast output voltage transition for SRAM yield improvement
Author :
Tseng, Chun-Yen ; Huang, Po-Chiun ; Wang, Li-Wen
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear :
2009
fDate :
16-18 Nov. 2009
Firstpage :
329
Lastpage :
332
Abstract :
This work presents a fully integrated linear regulator design that can dynamically assign the SRAM cell voltage to increase the read/write margin. To minimize the timing overhead between read/write mode switches, this design adopts two separate feedback loops for bias and load regulations. Individual optimization for each loop makes fast reference tracking and load regulation possible. To verify this concept, a prototype LDO is realized with a 1.8-V 0.18 ¿m CMOS. The output voltage can be freely set between 0.9 and 1.7-V. The measured transition speed is 48 ns/0.3 V. The maximum current efficiency is 94.7% under a 20 mA current loading.
Keywords :
CMOS memory circuits; SRAM chips; circuit feedback; voltage regulators; LDO; SRAM cell; bias regulation; current 20 mA; current efficiency; fast output voltage transition; fast reference tracking; feedback loops; fully integrated linear regulator design; load regulation; read-write margin; read-write mode switches; size 0.18 mum; timing overhead; voltage 0.9 V to 1.7 V; voltage 1.8 V; Current measurement; Feedback loop; Prototypes; Random access memory; Regulators; Switches; Timing; Tracking loops; Velocity measurement; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
Type :
conf
DOI :
10.1109/ASSCC.2009.5357161
Filename :
5357161
Link To Document :
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