DocumentCode
2723765
Title
A new procedure for weighted random built-in self-test
Author
Muradali, Fidel ; Agarwal, Vinod K. ; Nadeau-Dostie, Benoit
Author_Institution
VLSI Design Lab., McGill Univ., Montreal, Que., Canada
fYear
1990
fDate
10-14 Sep 1990
Firstpage
660
Lastpage
669
Abstract
It is proposed that a pseudorandom sequence and a single weighted random sequence be used to implement built-in self-test (BIST) efficiently in a large integrated scan circuit which would otherwise need an excessive pseudorandom test length. A method of determining the weight set and the approximate pseudorandom and weighted random test lengths, based on fast fault simulation tools, is suggested. By modifying specific scan cells, the BIST hardware conditionally generates the weighted stream locally, at specific input sites. A weighted control signal is used to regulate the proportion of weighted and pseudorandom inputs. Apart from determining that, in the cases examined, one weight set was sufficient for a notable decrease in test time, it was also noticed that a very coarse weight set (i.e. restricting biases to 0, 0.25, 0.5, 0.75, and 1) provides acceptable results. Using finer resolution within the weight set usually results in a slightly higher coverage, but at the expense of a much higher area overhead
Keywords
automatic testing; built-in self test; logic testing; random processes; BIST; automatic testing; fault simulation; integrated scan circuit; logic testing; pseudorandom sequence; scan cells; single weighted random sequence; weighted control signal; weighted random built-in self-test; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electronic mail; Fault detection; Hybrid power systems; Laboratories; Test pattern generators; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1990. Proceedings., International
Conference_Location
Washington, DC
Print_ISBN
0-8186-9064-X
Type
conf
DOI
10.1109/TEST.1990.114081
Filename
114081
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