Title :
Fluxless tin bonding of silicon chips to aluminum substrates
Author :
Hsu, Shou-Jen ; Sha, Chu-Hsuan ; Lee, Chin C.
Author_Institution :
Electr. Eng. & Comput. Sci., Mater. & Manuf. Technol., Univ. of California, Irvine, CA, USA
fDate :
May 29 2012-June 1 2012
Abstract :
The high thermal conductivity and light weight properties of aluminum (Al) make it a promising material in high power device packaging and automotive design applications. A primary challenge is its high coefficient of thermal expansion (CTE) of 23 ppm/°C. In this research, we investigated the possibility of surmounting this challenge by bonding large Si chips to Al substrates using fluxless tin (Sn). Si versus Al pair probably has the largest CTE mismatch among all bonded structures in electronic packaging. In experiments, 0.1μm Cr layer and 0.2 μm Cu layer were deposited on Al substrates, followed by an electroplated thicker 25 μm copper (Cu) layer. The Sn solder layer was then electroplated over the Cu followed immediately by thin (0.1 μm) silver (Ag) layer. The bonding process is entirely fluxless. The joint thickness was controlled either by bonding pressure or by Cu spacers. Microstructure and composition of the joints were studied under scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX). Despite the large CTE mismatch, the bonded structures did not break. This preliminary result suggests potential adaption of Al substrates in electronic packaging where Al is avoided because of its high CTE.
Keywords :
X-ray chemical analysis; aluminium; bonding processes; copper; electronics packaging; electroplating; elemental semiconductors; microprocessor chips; scanning electron microscopy; silicon; solders; thermal conductivity; tin; Al; CTE mismatch; Cu; Si; Sn; Sn solder layer; aluminum substrates; automotive design; chromium layer; copper layer; electronic packaging; electroplating; energy dispersive X-ray spectroscopy; fluxless tin bonding; high power device packaging; light weight properties; scanning electron microscopy; silicon chips; size 0.1 mum; size 0.2 mum; size 25 mum; thermal conductivity; thermal expansion coefficient; Bonding; Joints; Silicon; Soldering; Substrates; Tin;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4673-1966-9
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2012.6248978