Title :
Pipelined reduced-state sequence estimation
Author :
Haratsch, Erich F. ; Azadet, Kamran
Author_Institution :
Inst. for Integrated Circuits, Tech. Univ. Munchen, Germany
Abstract :
The throughput of reduced-state sequence estimation (RSSE) is limited by a substantially longer recursive loop than the add-compare-select function, which is the bottleneck of Viterbi decoding. This paper reformulates the RSSE algorithm to allow pipelining of the branch metric and decision-feedback computation. With this approach the critical path is shortened to the order of the add-compare-select function with only modest increase in hardware
Keywords :
VLSI; Viterbi decoding; feedback; local area networks; pipeline processing; sequential estimation; Gigabit Ethernet; RSSE algorithm; VLSI implementation; Viterbi decoding; add-compare-select function; branch metric; critical path; decision-feedback computation; pipelined reduced-state sequence estimation; recursive loop; throughput; AWGN; Bit error rate; Copper; Ethernet networks; Hardware; Intersymbol interference; Maximum likelihood estimation; Throughput; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Global Telecommunications Conference, 2000. GLOBECOM '00. IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-6451-1
DOI :
10.1109/GLOCOM.2000.891297
