Macro-testability and the VSP

Author

Mehtani, R. ; Baker, K. ; Huizer, C.M. ; Hynes, P.J. ; van Beers, J.

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1990

fDate

10-14 Sep 1990

Firstpage

739

Lastpage

748

Abstract

The authors describe a design-for-testability scheme and test generation for a digital video signal processing IC. The video signal processor (VSP) IC has an advanced multiprocessor architecture and is capable of executing 1400 MOPS (million operations per second) at an operating frequency of 27 MHz. The testability scheme developed makes full use of the macro-test concept. Several new methods for enhancing the macro-test concept are described. The testability scheme is shown to be efficient in terms of test costs and area overhead and is also scalable to the next generation of VSP ICs

Keywords

computer architecture; computerised picture processing; digital signal processing chips; integrated circuit testing; multiprocessing systems; video signals; 27 MHz; DSP chip; IC testing; area overhead; costs; macro-test; multiprocessor architecture; testability; video signal processor; Cities and towns; Computer architecture; Converters; Costs; Design for testability; Digital integrated circuits; Integrated circuit testing; Real time systems; Signal processing; Video signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1990. Proceedings., International

Conference_Location

Washington, DC

Print_ISBN

0-8186-9064-X

Type

conf

DOI

10.1109/TEST.1990.114090

Filename

114090