DocumentCode
2723952
Title
Design and assembly of a double-sided 3D package with a controller and a DRAM stack
Author
Liu, Xi ; Li, Ming ; Mullen, Don ; Cline, Julia ; Sitaraman, Suresh K.
Author_Institution
George W. Woodruff Sch. of Mech. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2012
fDate
May 29 2012-June 1 2012
Firstpage
1205
Lastpage
1212
Abstract
The microelectronic packaging field is moving into the third dimension for miniaturization, low power consumption, and better performance. In this paper, we present a double-sided flip-chip organic substrate with a memory controller on one side of the package, and 3D stacked disaggregated memory chips on the other side of the package. This design allows the controller to interface with the DRAM stack directly through the substrate providing the shortest possible interconnect path, and thus achieving the fastest signaling speed. However, this double-sided flip chip on organic substrate also causes yield, assembly, test, and reliability challenges. In order to optimize the assembly process, a sequential 3D finite-element model was developed to simulate the package assembly process. In these simulations, various assembly process sequences were simulated with different conditions and materials. In addition, a probing test model was also built to study the connectivity of the Land Grid Array (LGA) pin array with the PCB sockets. Results show that the careful selection of assembly steps and package materials are crucial for the successful package assembly and also important for the probing test.
Keywords
DRAM chips; finite element analysis; power consumption; printed circuits; semiconductor device metallisation; semiconductor device packaging; 3D finite-element model; 3D stacked disaggregated memory chips; DRAM stack; LGA pin array; PCB sockets; double-sided 3D package; double-sided flip-chip organic substrate; interconnection path; land grid array pin array; low power consumption; memory controller; microelectronic packaging field; package materials; reliability; Assembly; Ceramics; Flip chip; Memory management; Random access memory; Sockets; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location
San Diego, CA
ISSN
0569-5503
Print_ISBN
978-1-4673-1966-9
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2012.6248989
Filename
6248989
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