A quantization error minimization using DDS-DAC for wideband fractional-N frequency synthesizer

This work presents a quantization error minimization technique for a fractional-N frequency synthesizer. By using a direct digital synthesis phase accumulator as the fractional divider and a DAC as pulse conversion, the quantization error can be much smaller than the one by conventional ¿-¿ modulated multi-modulus divider. With small quantization error, dedicated compensation mechanism is no longer necessary for wide loop bandwidth applications. To demonstrate this concept, a prototype chip is realized with the 0.18 ¿m CMOS. The synthesizer consumes 31 mA under a single 1.8 V supply. With 1 MHz closed-loop bandwidth, the in-band noise is -94 dBc/Hz and the 3 MHz offset noise is -118 dBc/Hz for the 1.8 GHz output. The output exhibits 27 dB phase noise reduction. The settling time is 2 ¿s under a 35 MHz frequency step.