A charge pump current missmatch calibration technique for ΔΣ fractional-N PLLs in 0.18-μm CMOS

This work presents a charge pump (CP) calibration technique for a delta-sigma fractional-N phase-locked loop (ΣΔ-FNPLL). The proposed calibration method introduces an auxiliary path to the CP circuit and utilizes some interval within each reference cycle to detect the mismatch and then correct the up/down current difference. The proposed CP calibration is employed in the design of a 2.4-GHz ΣΔ-FNPLL. The experimental result has demonstrated that the in-band phase noise and fractional spurs are significantly reduced when the proposed CP calibration is activated. Fabricated in a TSMC 0.18-μm CMOS process, the whole ΣΔ-FNPLL consumes 23 mW from a 1.8-V supply.