• DocumentCode
    2724024
  • Title

    The dynamic reduction of fault simulation

  • Author

    Maamari, Fadi ; Rajski, Janusz

  • Author_Institution
    Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
  • fYear
    1990
  • fDate
    10-14 Sep 1990
  • Firstpage
    801
  • Lastpage
    808
  • Abstract
    Efficient strategies for selectively performing fault-free simulation, critical path tracing in fanout-free regions, and fault simulation of stem faults in a parallel pattern evaluation environment are presented and analyzed in an implementation-independent manner. The dynamic changes in the complexity of the fault simulation components as the fault simulation progresses and faults are detected are shown to be extremely significant. In particular, fault-free simulation tends quickly to become more expensive than both the critical path tracing within fanout-free regions and the explicit simulation of stem faults. In addition, the presence of redundant faults is shown to have an inhibiting effect on the reduction of the fault simulation complexity
  • Keywords
    digital simulation; fault location; logic testing; critical path tracing; dynamic reduction; fanout-free regions; fault simulation; parallel pattern evaluation environment; redundant faults; self hiddening; stem faults; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Fault detection; Laboratories; Logic testing; Performance evaluation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1990. Proceedings., International
  • Conference_Location
    Washington, DC
  • Print_ISBN
    0-8186-9064-X
  • Type

    conf

  • DOI
    10.1109/TEST.1990.114097
  • Filename
    114097