DocumentCode
2724091
Title
Advanced low profile PoP solution with embedded wafer level PoP (eWLB-PoP) technology
Author
Yoon, Seung Wook ; Caparas, Jose Alvin ; Lin, Yaojian ; Marimuthu, Pandi C.
Author_Institution
STATS ChipPAC Ltd., Singapore, Singapore
fYear
2012
fDate
May 29 2012-June 1 2012
Firstpage
1250
Lastpage
1254
Abstract
Current portable electronic products are driving component packaging towards 3D packaging technologies for integrating multiple memory die and application processors (AP). Among the 3D technologies, Package-on-Package (PoP) is increasingly becoming mainstream due to its flexibility of combination and sourcing. Moreover, device designs require functional integration of IC´s, especially in the 3rd dimension, hence driving new technology development towards making IC components “thin and thinner”. eWLB (embedded Wafer Level Ball Grid Array) has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. There is also great opportunity related to a 3D variation of eWLB which would allow for mounting of components or another package on the top surface with thinner profile and Package-on-Package (eWBL-PoP) technology. 3D PoP-eWLB is envisioned as an exciting technology which will open up the floodgates for system level integration utilizing very thin stacked eWLB packages as building blocks in mobile applications. This paper reports developments that are aimed to extend the low profile PoP application with eWLB + PoP technology. Test vehicle is designed and fabricated to demonstrate to be thin and 3D PoP solution for mobile and portable electronics. Assembly process details including laser ablation and interconnects process and mechanical characterizations are to be discussed with component and board level reliability results. Innovative package structures optimization that provide dual advantages of both form factor reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, package with multi layer redistribution (RDL) and 10um/10um line width/spacing is fabricated and implemented on eWLB platform. Successful reliability characterization results on low profile PoP package configurations are reported that demonstrate eWLB-PoP as a- enabling technology for miniaturized, low profile and cost-effective 3D PoP.
Keywords
ball grid arrays; integrated circuit interconnections; integrated circuit reliability; laser ablation; wafer level packaging; 3D packaging; application processors; assembly process; board level reliability; component packaging; eWLB-PoP technology; embedded wafer level PoP; embedded wafer level ball grid array; integrated circuit components; interconnection density; interconnects process; laser ablation; low profile PoP solution; mobile applications; multilayer redistribution; multiple memory die; package-on-package; portable electronic products; signal routing; Assembly; Laser ablation; Packaging; Performance evaluation; Reliability; Standards; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location
San Diego, CA
ISSN
0569-5503
Print_ISBN
978-1-4673-1966-9
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2012.6248995
Filename
6248995
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