Bridging faults and their implication to PLAs

A complete analysis of the bridging faults between gate outputs in FC (full complementary) MOS and PE (precharge evaluate) MOS is presented. It is shown that circuit design to force wired-AND or wired-OR effects in the presence of bridging faults leads to an adverse effect on noise margin, area, and speed. Hence, a functional testing is not desirable if FC MOS gates are employed, and the alternative method involving current testing should be used. In PE MOS gates, however, current testing is not possible, and, therefore, functional testing must be resorted to, despite the adverse side effects. The authors consider an area-efficient implementation of PLAs (programmable logic arrays) which uses both FC MOS and PE MOS logic, an implementation that is commonly used in VLSI designs. All possible classes of bridging faults in this implementation are identified and methods of detecting them are given