Complete self-test architecture for a coprocessor [cryptography]

A combination of a firmware-based and a hardware-based self-test architecture is chosen for the complete test of a coprocessor. The hardware approach is useful in testing completely embedded macrocells and supporting the self-test firmware, Four embedded macrocells were made self-testable by implementing well-known built-in self-test methods. The self-test architecture applied is of general applicability (linear feedback shift register). The remaining macrocells and the coordination of the various chip macrocells are tested by executing an on-chip firmware routine. By use of ordinary processor functions it is possible to reduce considerably the hardware overhead for implementing a complete self-test