Title :
A CMOS 6-mW 10-bit 100-MS/s two-step ADC
Author :
Chung, Yung-Hui ; Wu, Jieh-Tsorng
Author_Institution :
Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
A 10-bit 100-MS/s two-step ADC was fabricated using a 90 nm CMOS technology. To reduce power dissipation, the ADC uses latch-type comparators for signal digitalization and an open-loop amplifier for residue amplification. The linearity of the residue amplifier is enhanced by digital background calibration. The resolution of the comparators is improved by analog offset calibration. The ADC consumes 6mW from a 1V supply. Measured SNR and SFDR are 58.2 dB and 75 dB respectively. Measured ENOB is 9.34b. The FOM is 100 fJ per conversion-step.
Keywords :
CMOS digital integrated circuits; amplifiers; analogue-digital conversion; calibration; comparators (circuits); CMOS technology; SFDR; SNR; analog offset calibration; digital background; latch-type comparators; open-loop amplifier; power 6 mW; residue amplification; signal digitalization; size 90 nm; two-step ADC; word length 10 bit; CMOS technology; Calibration; Capacitors; Energy consumption; Error correction; Latches; Power amplifiers; Preamplifiers; Switches; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
DOI :
10.1109/ASSCC.2009.5357197
