• DocumentCode
    2724268
  • Title

    A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS

  • Author

    Chen, Yanfei ; Tsukamoto, Sanroku ; Kuroda, Tadahiro

  • Author_Institution
    Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama, Japan
  • fYear
    2009
  • fDate
    16-18 Nov. 2009
  • Firstpage
    145
  • Lastpage
    148
  • Abstract
    A 9 b 100 MS/s successive approximation register (SAR) ADC has been implemented in 65 nm CMOS, with an active area of 0.012 mm2. A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1 dB (8.53 ENOB) and consumes 1.46 mW from a 1.2 V supply, resulting in an FOM of 39 fJ/conversion-step.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; capacitors; CMOS; DAC switching energy efficiency; SAR ADC; differential capacitor arrays; power 1.46 mW; settling time; size 65 nm; successive approximation register; trilevel based charge redistribution; voltage 1.2 V; word length 9 bit; Bridge circuits; Capacitance; Clocks; Energy efficiency; Logic circuits; Low voltage; Solid state circuits; Switched capacitor circuits; Switches; Switching circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4244-4433-5
  • Electronic_ISBN
    978-1-4244-4434-2
  • Type

    conf

  • DOI
    10.1109/ASSCC.2009.5357199
  • Filename
    5357199
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2724268