• DocumentCode
    2724306
  • Title

    3D-interconnect approach for high end electronics

  • Author

    Das, Rabindra N. ; Egitto, Frank D. ; Lauffer, John ; Bonitz, Barry ; Wilson, Bill ; Marconi, Francesco ; Poliks, Mark D. ; Markovich, Voya R.

  • Author_Institution
    Endicott Interconnect Technol., Inc., Endicott, NY, USA
  • fYear
    2012
  • fDate
    May 29 2012-June 1 2012
  • Firstpage
    1333
  • Lastpage
    1339
  • Abstract
    This paper presents 3D-interconnect technology to produce a variety of structures and packages suitable for high end electronics. 3D-interconnect can join different size multiple rigid structures for rigid-rigid constructions. For example, a high density circuit card and a low end printed wiring board were attached using 3D-interconnect to achieve functionality similar to a complex board. Various sub-composites, signal-power cores, were laminated with paste filed joining cores (0S/1P) or joining layers (0S/0P) to improve wiring density of a package. A 3D “Package-Interposer-Package” (PIP) integration method was used to attach multiple assembled substrates. An example of a structure consisting of seven stacked substrates attached using PIP approach is given. The PIP approach can provide for replacement, repair, or upgrade of individual substrates in the stack, beneficial for processing of complex, expensive product. In addition 3D-micro bump technology was developed as am alternative to solder based, pasteless 3D interconnects. A variety of materials and processes, including paste, Cu micro pillars, and solder-based micro-bumps were developed for 3D-interconnects. Overall, the present work describes an integrated approach to develop 3D interconnect constructions on various complex package, stacked package, or stacked die packaged configurations.
  • Keywords
    semiconductor device metallisation; semiconductor device packaging; 0S-0P; 0S-1P; 3D package-interposer-package integration method; 3D-interconnect approach; Cu micro pillars; PIP integration method; complex processing; expensive product; high density circuit card; high end electronics; low end printed wiring board; paste filed joining cores; rigid-rigid constructions; signal-power cores; size multiple rigid structures; solder-based 3D micro-bump technology; Complexity theory; Dielectrics; Integrated circuit interconnections; Joining processes; Silicon; Substrates; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
  • Conference_Location
    San Diego, CA
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4673-1966-9
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2012.6249007
  • Filename
    6249007