TSV-based decoupling capacitor schemes in 3D-IC

In this study, the scheme of a TSV-based decoupling capacitor stacked chip (DCSC) is proposed as a decoupling capacitor scheme to be possibly implemented in 3D-IC. The conventional decoupling capacitor schemes to be applied in a 3D-IC system include on-chip NMOS capacitors and package-level decoupling capacitor solutions. The proposed TSV-based DCSC scheme that can improve a disadvantage (i.e., relatively small capacitances) in the conventional on-chip NMOS capacitors and a limitation in package-level decoupling capacitor solutions represents excellent 3D-PDN (power delivery network) performance. In the comparison of the proposed TSV-based DCSC scheme with the conventional decoupling capacitor schemes, the propose scheme shows a similar level to the chip PDN that implements on-chip NMOS capacitors more than 10 nF and an SSN suppression effect of 93% compared to that of on-package decoupling capacitors. However, in the case of the on-chip NMOS capacitors, as an additional chip area, few mm × few mm, is required to ensure a capacitance of 10 nF, it is a scheme that has a limitation in increasing chip sizes. In conclusion, the proposed TSV-based DCSC is a decoupling capacitor solution that represents the most appropriate and excellent PDN performance in a 3D-IC system.