Title :
A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance
Author :
Huang, Guan-Ying ; Liu, Chun-Cheng ; Lin, Ying-Zu ; Chang, Soon-Jyh
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan
Abstract :
This paper reports a successive-approximation analog-to-digital converter (ADC) with low input capacitance. The 10-bit prototype is fabricated in a 0.13-¿m CMOS process. Compared to conventional successive approximation ADCs, the proposed ADC reduces the input capacitance to 1.2 pF for 10-bit resolution. At 12 MS/s and 1.2-V supply, this ADC consumes 0.32 mW and achieves an SNDR of 50.89 dB, resulting in an FOM of 95 fJ/Conversion-step.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; low-power electronics; 10-bit resolution; CMOS process; SAR ADC; SNDR; capacitance 1.2 pF; power 0.32 mW; size 0.13 mum; successive approximation ADC; successive approximation analog-to-digital converter; successive approximation register ADC; voltage 1.2 V; Analog-digital conversion; Capacitance; Capacitors; Clocks; Logic; Prototypes; Sampling methods; Solid state circuits; Switches; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
DOI :
10.1109/ASSCC.2009.5357202
