A 10Gb/s inductorless quarter-rate clock and data recovery circuit in 0.13um CMOS

A 10 Gb/s inductorless quarter-rate clock and data recovery (CDR) circuit is presented. In this CDR circuit, a triggering generator is proposed to realize the quarter-rate operation. Owing to the quarter-rate operation and the absence of inductors, this CDR circuit achieves low power consumption and small area simultaneously. This 10 Gb/s quarter-rate CDR circuit has been fabricated in a 0.13 um CMOS process. It recovers the data and clock within 5 bits. The measured peak-to-peak jitter of the recovered data and clock is 32.22 ps and 30.7 ps, respectively. The chip area including a PLL and a dummy GVCO is 0.2 mm². This CDR circuit consumes 122.5 mW excluding output buffers from a supply voltage of 1.5 V.