A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier

8 T bit-cells hold great promise for overcoming device variability in deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture and circuits with minimal area overhead to allow column-interleaving while eliminating the half-select problem. This enables sense-amplifier sharing and soft-error immunity. A reference selection loop is designed and implemented in the column circuitry. By choosing one of the two reference voltages for each sense-amplifier in a pseudo-differential scheme, selection loop effectively reduces input offset. 8 T test array fabricated in 45 nm CMOS achieves functionality from 1.1 V to below 0.5 V. Test chip operates at 450 MHz at 1.1 V and 5.8 MHz at 0.5 V while consuming 12.9 mW and 46 ¿W respectively.