Practical partitioning for testability with time-shared boundary scan

The authors present a partitioning method for practical circuits composed of a mixture of very complex and very simple components. Specifically, attention is given to circuits containing a mixture of very complex devices, such as RAMs, and simple devices, such as basic states. A partitioning tool, PTOOL, that can be applied with equal effectiveness at the IC and PCB (printed circuit board) levels is introduced. The partitioning is influenced. in part, by the type (function) of components that make up the target circuit. Components requiring different test strategies are isolated in separate subsystems. PTOOL also forms subsystems such that the deepest embedded component can be accessed after a maximum of N gate levels. In addition, a number of `good practice´ partitioning criteria are incorporated. For example, under certain conditions. deeply embedded flip-flops can be easily tested by testing the surrounding circuits without the use of a scan chain. PTOOL recognizes such conditions and avoids unnecessary partitioning costs. Once the circuit is partitioned, each subsystem is accessed by an internal boundary scan. The boundary scan is centered around an input test bus and an output test bus, which are time-shared by the various subsystems. The time-shared architecture significantly reduces the amount of test serialization and test overhead