Chip-last fan-out package with embedded power ICs in ultra-thin laminates

The demand for ultra-miniaturized mobile electronics systems has placed stringent requirements on the form-factor, especially thickness, of electronic modules. A novel technology to enable embedding in 1 or 2 metal layer substrates using chip-last technology was introduced previously [1]. This paper focuses on first ever demonstration of chip-last embedding of functional dies in 1-2 metal layer thin core substrates, to achieve form factor and performance comparable to wafer level fan-out with improved yield, cycle time reduction, cost, testability and thermal management. Ultra-slim modules were obtained as a result of embedding thin-chips within the core instead of the build-up layers reported previously [2]. Performance of chip-last embedded actives has been successfully demonstrated previously [3] using low power RF ICs. Embedding power management ICs (PMIC), however, not only challenges high power dissipation capabilities of chip-last fan-out package but also its high current carrying capability, with many I/Os drawing ~1A current. Since the embedded PMIC is rated at 2.3W dissipation, finite element modeling (FEM) was carried out to simulate thermal performance of the package under steady state conditions. Assuming uniform distribution of the 2.3W over the entire PMIC, FEM simulations depicted a maximum temperature of ~52°C on the top of the embedded IC, a rise of ~27°C from the base temperature of 25°C, indicating the heat dissipation to be a non-issue. Module substrates were built using 100μm BT as core and ABF as the cavity layer dielectric. Thinned functional ICs were assembled in the laser-ablated cavities using previously demonstrated Cu-Cu thermo-compression bonding [4, 5]. The resulting module thickness with the embedded IC was ~200μm, a reduction of more than 55% from the incumbent. The demonstrated ultra-thin laminate based fan-out package with embedded PMIC uses a simple fabrication process flow making it a manu- acturing-friendly and cost effective solution. Therefore, the low layer count chip-last embedding technology has the potential to achieve ultra-miniaturization for future embedded sub-systems and systems.