Title :
An empirical relationship between test transparency and fault coverage
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
The concept of test transparency was used to analyze the reject data from different fault coverage soft bins. The device used in the study was a gate array with 12.5 K equivalent logic gates. As additional vectors were generated they were isolated into separate modules within the sort program. The sort program shell was altered to provide a soft bin count of the number of failures incurred within each module. This information was then uploaded automatically into the manufacturing database. The results presented are based on functional test results from over 350000 dice. It is shown that Boolean testing can be represented as a linear relationship between test transparency and fault coverage. The linear coefficients are sensitive to the defect type for the stuck-at model fault coverage. The linear coefficients are also sensitive to the fault vector generation methodology
Keywords :
Boolean algebra; automatic testing; electronic engineering computing; failure analysis; fault location; logic arrays; logic testing; manufacturing data processing; modules; production testing; Boolean testing; automatic testing; fault coverage; fault vector generation; functional test; gate array; linear coefficients; logic gates; manufacturing database; modules; soft bin count; sort program shell; stuck-at model; test transparency; Benchmark testing; Circuit faults; Circuit testing; Displays; Engines; Fault detection; Logic devices; Logic testing; Semiconductor device modeling; Vectors;
Conference_Titel :
Test Conference, 1990. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-9064-X
DOI :
10.1109/TEST.1990.114123