FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers

Field programmable gate array (FPGA) is widely used for efficient hardware realization of digital signal processing (DSP) circuits and systems. Finite impulse response (FIR) filter is the core of any DSP and communication systems. To improve the performance of FIR filter, an efficient multiplier is required. Wallace tree and Vedic multipliers are used in this paper for the implementation of sequential and parallel microprogrammed FIR filter architectures. The designs are realized using Xilinx Virtex-5 FPGA. FPGA implementation results are presented and analyzed. Based on the implementation results, sequential FIR filter using Wallace tree multiplier/carry skip adder combination proves to be more efficient as compared to other multiplier/adder combinations.