Marginal fault diagnosis based on e-beam static fault imaging with CAD interface

Author

Kuji, Norio ; Matsumoto, Kiyoshi

Author_Institution

NTT LSI Lab., Kanagawa, Japan

fYear

1990

fDate

10-14 Sep 1990

Firstpage

1049

Lastpage

1054

Abstract

A novel image-based diagnostic method is proposed for an e-beam tester. In this method, a static-fault-imaging (SFI) technique and a navigation map for fault tracing are introduced. The SFI technique, in which a DC e-beam is used, enables fast acquisition of images without any additional hardware. Then, guided by the navigation map derived from CAD (computer-aided-design) data, marginal time faults can be easily pinpointed. The proposed method is applied to a 19 K-gate CMOS logic LSI circuit, and a marginal timing fault is located in about one-tenth the turn-around time of the conventional waveform-based method. It is concluded that this method should be very useful for the diagnosis of marginal faults related to supply voltage and temperature

Keywords

CMOS integrated circuits; automatic testing; circuit CAD; electron beam applications; integrated circuit testing; logic CAD; logic testing; 19 K-gate CMOS logic LSI circuit; CAD interface; DC; automatic testing; e-beam static fault imaging; e-beam tester; fault tracing; image-based diagnostic method; logic testing; marginal fault diagnosis; marginal time faults; navigation map; static fault location; static-fault-imaging; supply voltage; temperature; CMOS logic circuits; Circuit faults; Fault diagnosis; Hardware; Large scale integration; Navigation; Temperature; Testing; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1990. Proceedings., International

Conference_Location

Washington, DC

Print_ISBN

0-8186-9064-X

Type

conf

DOI

10.1109/TEST.1990.114129

Filename

114129