TDRC-a symbolic simulation based design for testability rules checker

A symbolic simulation methodology that can be used to verify a set of standard scan-path-based, ad hoc, and boundary-scan design-for-testability (DFT) rules is proposed, and a DFT rule checker, TDRC (testability design rule checker), that uses this methodology is described. In this methodology, symbolic tokens are used to represent the types of signals applied to the primary inputs of the circuit, and, in a process analogous to simulation, these tokens are propagated through the circuit using a set of simulation rules. A check is then made to verify that the required tokens have been propagated to each scan element and that only allowed tokens have reached particular element and circuit ports. The proposed simulation methodology differs from previous path-tracing approaches in that symbolic tokens are propagated to the output of an object, possibly in modified form, depending on the other tokens reaching both the inputs and the logical function of the object. TDRC has been successfully used to identify real problems in real ASIC (application-specific integrated-circuit designs)