DocumentCode
2724567
Title
Testable design and support tool for cell based test
Author
Ogihara, Takuji ; Koseko, Yasushi ; Yonemori, Genichi ; Kawai, Hiroyuki
Author_Institution
Mitsubishi Electr. Corp., Kanagawa, Japan
fYear
1990
fDate
10-14 Sep 1990
Firstpage
1065
Lastpage
1071
Abstract
The authors describe a testable design method and the corresponding support tool for testing large-scale cells embedded on LSIs. The testable design method requires very little extra hardware to increase testability. The support tool enables users to test the large-scale cells by using already prepared test patterns. Consequently, test generation, and fault simulation times are decreased
Keywords
cellular arrays; digital simulation; fault location; integrated circuit testing; integrated logic circuits; large scale integration; logic testing; LSI; fault simulation times; large-scale cells; logic testing; support tool; test generation; test patterns; testable design; Circuit faults; Circuit testing; Costs; Degradation; Design methodology; Hardware; Large-scale systems; Logic design; Logic testing; Sequential analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1990. Proceedings., International
Conference_Location
Washington, DC
Print_ISBN
0-8186-9064-X
Type
conf
DOI
10.1109/TEST.1990.114131
Filename
114131
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