Development of Through Silicon Via (TSV) interposer for memory module flip chip package

With the trend of microelectronics packaging toward more functionality, high performance and smaller form factor, the product is required to deliver more I/Os and better electrical characteristics under a minimum module system. Therefore, a 3D IC integration System in Package (SiP) with passive Through Silicon Via (TSV) interposer technology is proposed to provide high density and heterogeneous integration needed for such requirement. Due to the Coefficients of Thermal Expansion (CTE) mismatch between materials, thermal-mechanical stress and warpage are induced during Through Silicon Interposer (TSI) fabrication process, which may affect TSV crack or Controlled Collapse Chip Connection (C4) bump crack after TSI bonding to organic substrate process. Therefore, this work is a step by step process simulation with various design parameters by finite element method (FEM) to investigate stress and warpage behaviors of processing effect. For both full array dummy bumps layout and thinner top chips are to reduce micro-bump stress. Also, low CTE organic substrate core, high CTE mold compound and thinner top chips perform lower package warpage. Finally, this paper aims to provide a guideline to designer for 3D IC integration SiP with passive TSV interposer structure by using the finite element models.