Title :
Via wearout detection with on chip monitors
Author :
Ahmed, Fahad ; Milor, Linda
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
The delays of paths in a chip can be monitored to detect via voiding. This work relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The sensitivity of the trigger point as a function of the failure distribution parameters and the path length has been investigated. A circuit has been designed to detect the onset of chip failure due to via voiding.
Keywords :
delays; detector circuits; electromigration; failure analysis; jitter; logic gates; NAND gates; NOR gates; delay detection circuit; electromigration; failure distribution parameters; inverter chain; jitter; path delays; trigger point sensitivity; voiding; wearout detection; Circuit faults; Computer displays; Condition monitoring; Costs; Degradation; Delay; Design for testability; Electrical fault detection; Power dissipation; Ring oscillators;
Conference_Titel :
Advances in sensors and Interfaces, 2009. IWASI 2009. 3rd International Workshop on
Conference_Location :
Trani
Print_ISBN :
978-1-4244-4708-4
Electronic_ISBN :
978-1-4244-4709-1
DOI :
10.1109/IWASI.2009.5184787
