Title :
Plasma etch and low temperature PECVD processes for via reveal applications
Author :
Thomas, Dave ; Buchanan, Keith ; Griffiths, Hefin ; Crook, Kath ; Carruthers, Mark ; Ansell, Oliver ; Archard, Dan
Author_Institution :
SPTS Technol., Newport, UK
fDate :
May 29 2012-June 1 2012
Abstract :
This paper will focus on 300mm etch and CVD technologies for via reveal (VR) processing. Data on silicon etching will show that etch rates >;5μm/min, with uniformity ±2.5% and selectivity to the liner oxide around ~200:1 can be achieved on bonded TSV wafers. A novel end-point detection method will also be presented allowing control of the reveal height. The ability to tune the uniformity from centre fast to edge fast will also be covered. A range of stable, repeatable, dielectric films will be presented having a deposition temperature <;180°C and no moisture uptake. These films will also be shown to have highly conformal via tip coverage and excellent electrical properties, with breakdown voltages >;10 MV/cm and leakage current densities <;1E-9 A/cm2 at 2MV/cm.
Keywords :
dielectric thin films; electric breakdown; elemental semiconductors; leakage currents; plasma CVD; silicon; three-dimensional integrated circuits; Si; bonded TSV wafers; breakdown voltages; deposition temperature; dielectric films; electrical properties; end-point detection; leakage current densities; low temperature PECVD process; plasma etch; silicon etching; via reveal processing; wavelength 300 nm; Copper; Films; Plasma temperature; Silicon; Sulfur hexafluoride; Temperature; Through-silicon vias;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4673-1966-9
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2012.6249061
