DocumentCode :
2725344
Title :
ParSPIKE-a parallel DSP-accelerator for dynamic simulation of large spiking neural networks
Author :
Wolff, Carsten ; Hartmann, Georg ; Rückert, Ulrich
Author_Institution :
Paderborn Univ., Germany
fYear :
1999
fDate :
1999
Firstpage :
324
Lastpage :
331
Abstract :
The fast simulation of large networks of spiking neurons is a major task for the examination of biology inspired vision systems. Networks of this type are labelling features by synchronization of spikes and there is strong demand to simulate those effects in a real world environment. Because of the quite complex calculations for one model neuron the simulation of thousands or millions of these neurons is not efficient on existing hardware platforms. In order to simulate closer to the real time requirement, it is necessary to implement a dedicated hardware. Our aim is a hardware system mainly consisting of standard components which is as flexible as possible concerning the model neuron but as specialized as necessary to meet our performance requirements. Thus we decided to implement a parallel system with Digital Signal Processors (DSP) offering a large on-chip-memory. One main task of this work is the optimization of the simulation algorithm for the neurons distributed to the DSP which means the sequential part of simulation. This optimization benefits from the fact that there is only a very low percentage of simultaneously active neurons in vision networks. For communication between the nodes only spikes are distributed via a spike switching network. Processing of the network topology is realized by two different concepts. One idea is to compute the synapses autonomously on the processing node by representing a regular connection scheme with one connection mask for many neurons. Additional connections requiring adaptability and irregular connection schemes are stored in a shared memory. To avoid a bottleneck a synapse caching is used within each processing node. This paper describes the architecture of a DSP accelerator and shows the advantages with simulation results from a typical large vision network
Keywords :
computer vision; digital signal processing chips; neural chips; parallel architectures; synchronisation; ParSPIKE; adaptability; biology inspired vision systems; connection mask; dedicated hardware; digital signal processors; dynamic simulation; irregular connection schemes; large spiking neural networks; large vision network; network topology; on-chip-memory; parallel DSP-accelerator; processing node; regular connection scheme; simulation algorithm; spike switching network; synapses; synchronization; Biological system modeling; Computational biology; Digital signal processing; Digital signal processors; Hardware; Labeling; Machine vision; Neurons; Signal processing algorithms; Systems biology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on
Conference_Location :
Granada
Print_ISBN :
0-7695-0043-9
Type :
conf
DOI :
10.1109/MN.1999.758882
Filename :
758882
Link To Document :
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