DocumentCode
2725437
Title
Line Width Roughness effects on device performance: The role of the gate width design
Author
Constantoudis, V. ; Gogolides, E. ; Patsis, G.P.
Author_Institution
Inst. of Microelectron., NCSR Demokritos, Aghia Paraskevi, Greece
fYear
2010
fDate
16-19 May 2010
Firstpage
265
Lastpage
268
Abstract
The role of the gate width in the effects of Line Width Roughness (LWR) on transistor performance is investigated. Two mathematical results regarding the statistical nature of LWR are presented and discussed. Exploiting the implications of these results through a 2D modeling approach, we indicate that, for fixed LWR, transistors with large gate widths seem to mitigate the degradation effects of LWR on transistor performance.
Keywords
CMOS integrated circuits; MOSFET; statistical analysis; 2D modeling approach; CMOS transistors; MOSFET; degradation effect mitigation; gate width design; line width roughness effects; Algorithm design and analysis; Degradation; Leakage current; Lithography; MOSFETs; Metrology; Microelectronics; Resists; Semiconductor device modeling; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics Proceedings (MIEL), 2010 27th International Conference on
Conference_Location
Nis
Print_ISBN
978-1-4244-7200-0
Type
conf
DOI
10.1109/MIEL.2010.5490486
Filename
5490486
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