Teaching top-down design using VHDL and CPLD

The paper presents a teaching experience in using VHDL and CPLD in the senior digital design course. The course focuses on teaching the top-down design methodology through hands-on experiments. The industrially available tools-Maxplus2, made possible through Altera´s University Program, provide students with a smooth transition from academic concepts to industrial practice. VHDL, the industrial standard language (IEEE-1076), is used as the design entry. Thus the students are forced to learn the practical aspect of writing a synthesizable VHDL code. The hands-on weekly projects are exercised on the integrated CPLD design tool which has VHDL, compiler, logic synthesizer, functional and timing simulator, floor plan editor and programmer. With the help of programmable devices, students can bypass the timing period for IC fabrication and obtain ASIC designs after the devices have been programmed. The VHDL design entry in Maxplus2 is ideal for teaching top-down design methodology. Translating from a given algorithmic state machine (ASM) chart to a synthesizable and efficient VHDL code is presented. Exploiting the VHDL constructs to make a design reusable is demonstrated through examples. In this course, students learn how to partition a complex design into small components and focus on higher level of abstraction and hierarchy in design description which have become desirable to digital systems designers