Title :
Design and process development of a stacked SRAM memory chip module with TSV interconnection
Author :
Ma, Shenglin ; Sun, Xin ; Zhu, Yunhui ; Zhu, Zhiyuan ; Cui, Qinghu ; Chen, Meng ; Xiao, Yongqiang ; Chen, Jing ; Miao, Min ; Lu, Wengao ; Jin, Yufeng
Author_Institution :
Nat. Key Lab. of Sci. & Technol. on Micro/Nano Fabrication, Peking Univ., Beijing, China
fDate :
May 29 2012-June 1 2012
Abstract :
In this paper, a stacked SRAM chip module is presented and simulation results are demonstrated. A novel 3D integration process is presented and challenging issues are addressed. With this novel process, there´s no need to do grinding/polishing of copper overburden after filling of TSV by copper electroplating. Copper microbumps will be formed directly on the active side in the filling of TSV by copper electroplating while the ones on the backside will be formed with backside releasing process. A test run is carried out with this novel process and a 4-layer stacked chip module is successfully fabricated.
Keywords :
SRAM chips; copper; electroplating; integrated circuit design; integrated circuit interconnections; three-dimensional integrated circuits; 3D integration process; 4-layer stacked chip module; TSV filling; TSV interconnection; backside releasing process; copper electroplating; copper microbumps; copper overburden grinding-polishing; stacked SRAM memory chip module; Copper; Filling; Resists; SRAM chips; Through-silicon vias; Tin;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4673-1966-9
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2012.6249101
