Title :
Chip to wafer direct bonding technologies for high density 3D integration
Author :
Sanchez, L. ; Bally, L. ; Montmayeul, B. ; Fournel, F. ; Dafonseca, J. ; Augendre, E. ; Cioccio, L. Di ; Carron, V. ; Signamarcheix, T. ; Taibi, R. ; Mermoz, S. ; Lecarpentier, G.
Author_Institution :
Leti, CEA, Grenoble, France
fDate :
May 29 2012-June 1 2012
Abstract :
We demonstrate chip to wafer assembly based on aligned Cu-Cu direct bonding. A collective die surface preparation for direct bonding has implemented to develop dies direct bonding, defect free. An accurate pick and place equipment was adapted to ensure a particle free environment. After a damascene-like surface preparation, chips were bonded with less than 1μm misalignment. 400°C bonded daisy chains on die to wafer structure are perfectly ohmic. Concurrently, to overcome speed limitation of pick and place technique, a self-assembly technique chip is developed. This technique is based on capillary effect for self alignment and direct bonding for assembly. A less than 1 μm alignment accuracy and a 90 per cent self assembly process yield are obtained.
Keywords :
integrated circuit bonding; self-assembly; three-dimensional integrated circuits; Cu-Cu; aligned direct bonding; bonded daisy chains; capillary effect; chip to wafer assembly; chip to wafer direct bonding technologies; collective die surface preparation; damascene-like surface preparation; high density 3D integration; particle free environment; pick and place equipment; process yield; self alignment; self-assembly technique chip; speed limitation; temperature 400 C; wafer structure; Assembly; Bonding; Cleaning; Contamination; Copper; Silicon; Surface treatment;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4673-1966-9
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2012.6249108