Temperature dependence of the 2D electron transport in Si accumulation layers

Author

Gutiérrez-D, Edmundo A. ; Rodriguez-T, Rodrigo

Author_Institution

Dept. of Electron., INAOE, Puebla

fYear

2006

fDate

26-28 April 2006

Firstpage

23

Lastpage

26

Abstract

This paper introduces an analysis and simulation of electron transport in accumulation layers from 300 K down to 4.2 K. The analysis, modeling, and simulation are confirmed with experimental results of an n-well gated resistor. The doping and gate oxide thickness dependence of the thickness of the accumulation layer is also analyzed and simulated. A model that accounts for all these variables is presented. The simulations are performed with PISCES, MINIMOS-NT, and a proprietary simulator. At 4.2 K a quasi-CMOS circuit is validated with a simple gated resistor

Keywords

CMOS integrated circuits; MOSFET; cryogenic electronics; electron mobility; semiconductor device models; semiconductor doping; 2D electron transport; 300 to 4.2 K; MINIMOS-NT; PISCES; Si; accumulation layers; doping; gate oxide thickness; n-well gated resistor; quasi-CMOS circuit; Analytical models; Circuit simulation; Doping; Electrons; Equations; MOSFETs; Resistors; Semiconductor process modeling; Temperature dependence; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, Proceedings of the 6th International Caribbean Conference on

Conference_Location

Playa del Carmen

Print_ISBN

1-4244-0041-4

Electronic_ISBN

1-4244-0042-2

Type

conf

DOI

10.1109/ICCDCS.2006.250830

Filename

4016859