Sporadic effect of leadscan machine to CMOS ESD low yielding lots

Integrated circuit manufacturing data history shows that Complementary Metal Oxide Semiconductor(CMOS) is one of the most Electrostatic Discharge (ESD) susceptible product technology. Sporadic low yielding lots on CMOS devices were analyzed as ESD failure related. After narrowing down the potential sources of ESD failures on the manufacturing process and identified the Back-End leadscan process as the most probable source of failure, further studies were conducted in this area to zero-out the "red-x". Process mapping, B vs C comparative study and a factorial experiment were performed, statistical tools were utilized and the root cause was identified and corrected. Implementation of the recommended corrective action resulted in elimination of sporadic ESD low yielding lots on CMOS devices and 62% reduction on ESD electrical gate failures.