Parallel pass based BPC design in JPEG2000

Author

Yoon, Ki Tae ; Park, Kun Ho ; Kwak, Chang Sub ; Choi, Jun Rim ; Han, Seung Soo

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Kyungpook Nat. Univ., Daegu, South Korea

Volume

4

fYear

2009

fDate

20-22 Nov. 2009

Firstpage

440

Lastpage

443

Abstract

JPEG2000 will be the international standard to continuous-tone still image coding in next generation. JPEG2000 algorithm is different from JPEG algorithm in filtering and entropy coding. In this thesis, we propose BPC hardware design based on parallel pass to improve performance. Hardware module which performs the bit plane coding (BPC) operation is designed by Verilog-HDL and synthesized by QuartusII. As a result of implementing BPC hardware, a speed gain of about 2 times is achieved when a process did BPC by based on serial pass.

Keywords

hardware description languages; image coding; BPC design; BPC hardware design; JPEG2000; QuartusII; Verilog-HDL; bit plane coding; continuous-tone still image coding; entropy coding; parallel pass; Buffer storage; Computer science; Discrete cosine transforms; Discrete wavelet transforms; Encoding; Entropy coding; Filtering algorithms; Hardware design languages; Image coding; Transform coding; BPC; EBCOT; JPEG2000; Parallel pass; Tier-1; bit plane coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Computing and Intelligent Systems, 2009. ICIS 2009. IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-4754-1

Electronic_ISBN

978-1-4244-4738-1

Type

conf

DOI

10.1109/ICICISYS.2009.5357652

Filename

5357652