DocumentCode
2727234
Title
A Low-Jitter Phase-Locked Loop with a Discriminator-Aided Edge Detector
Author
Lu, Chih-Wen ; Leong, Man Fai
Author_Institution
Dept. of Electr. Eng., Nat. Chi Nan Univ., Puli
fYear
2006
fDate
26-28 April 2006
Firstpage
315
Lastpage
318
Abstract
A phase-locked loop (PLL), in which the ripple in the control voltage is suppressed to minimize the output phase jitter, is proposed. A discriminator-aided edge detector is added in the PLL to switch the outputs of the loop filter to reduce the ripple. The proposed PLL and the conventional circuit have been implemented in a 0.35-mum CMOS process. Compared with the conventional PLL, the rms jitter is reduced from 19.0 ps to 18.3 ps and the peak-to-peak jitter is reduced from 148.2 ps to 139.1 ps
Keywords
CMOS analogue integrated circuits; discriminators; jitter; peak detectors; phase locked loops; 0.35 micron; CMOS process; PLL; discriminator-aided edge detector; loop filter; low-jitter; peak-to-peak jitter; phase-locked loop; Capacitors; Charge pumps; Detectors; Filters; Jitter; Phase detection; Phase locked loops; Switches; Voltage control; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Devices, Circuits and Systems, Proceedings of the 6th International Caribbean Conference on
Conference_Location
Playa del Carmen
Print_ISBN
1-4244-0041-4
Electronic_ISBN
1-4244-0042-2
Type
conf
DOI
10.1109/ICCDCS.2006.250880
Filename
4016909
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