Safe Path-Based Hierarchical Functional Timing Analysis by Considering Block Arrival Times

Timing verification of current designs demands efficient algorithms able to cope with the design complexity. Hierarchical descriptions provide a natural division of a design and thus it may be explored to reduce the complexity of the timing verification problem. Functional timing analysis (FTA) is a vector-independent approach that takes into account temporal and logical relations within the circuits to find a tight upper bound on circuit delay. However, flat-mode FTA is applicable only to moderate size designs. FTA of complex designs must explore hierarchy. In this paper we show how to apply ATPG-based FTA algorithms to hierarchical descriptions in order to obtain safe delay estimates and shorter execution times